Kou Tei
11Patents
2h-index
23Co-inventors
46Inventor score
Filing activity: Oct 7, 2014 → Jul 3, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9318204B1 | Non-volatile memory and method with adjusted timing for individual programming pulses | Physics | 5 | Active |
| US11139022B1 | Source line voltage control for NAND memory | Physics | 2 | Active |
| US10984877B1 | Multi BLCS for multi-state verify and multi-level QPW | Physics | 2 | Active |
| US10971209B1 | VHSA-VDDSA generator merging scheme | Physics | 2 | Active |
| US11521675B1 | Block-dependent cell source bounce impact reduction in non-volatile memory | Electricity | 1 | Active |
| US11222694B1 | Reference current generator control scheme for sense amplifier in NAND design | Physics | 1 | Active |
| US12057175B2 | Memory apparatus and method of operation using state dependent strobe tier scan to reduce peak ICC | Electricity | 0 | Active |
| US11798638B2 | Mitigating neighbor interference to select gates in 3D memory | Electricity | 0 | Active |
| US12361984B2 | Noise reduction in sense amplifiers for non-volatile memory | Physics | 0 | Active |
| US11881266B2 | Neighbor bit line coupling enhanced gate-induced drain leakage erase for memory apparatus with on-pitch semi-circle drain side select gate technology | Electricity | 0 | Active |
| US11978516B2 | Dynamic sense amplifier supply voltage for power and die size reduction | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.