Circuit prearranged heat dissipation embedded packaging structure and manufacturing method thereof
US12002734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2021 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Jul 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/2518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit prearranged heat dissipation embedded packaging structure according to an embodiment of the present disclosure includes at least one chip and a support frame surrounding the at least one chip. The support frame may include a via pillar passing through the support frame in the height direction, a first wiring layer on a first surface of the support frame, and a heat dissipation layer on the back face of the chip. The first wiring layer is flush with or higher than the first surface, the first wiring layer is in conductive connection with the heat dissipation layer, a gap between the chip and the frame is completely filled with the dielectric material, a second wiring layer is formed on a terminal face of the chip, and the second wiring layer is in conductive connection with the first wiring layer through the via pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.