Interconnection structure and semiconductor package including the same
US12009288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2021 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Sep 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.