Multi-layer feature fill
US12014928B2 · kind B2 · utility
1Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2019 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Feb 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described herein are methods and apparatuses for filling semiconductor substrate structures with conductive material. The methods involve depositing multi-layer bulk metal films in structures with one or more deposition conditions changed when transitioning from layer-to-layer. The methods result in high fill quality, high throughput, low precursor consumption, and low roughness. Multi-station chambers to perform the methods are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.