Semiconductor structure and method for forming the same
US12029044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2023 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Mar 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.