Semiconductor devices including gate structures with gate spacers
US12034056B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 9, 2021 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Apr 8, 2042 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion. The lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and comprises a first layer and a second layer. The first layer is in contact with a first portion of the sidewall and the second layer is in contact with a second portion of the sidewall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.