Liner-free resistance contacts and silicide with silicide stop layer
US12040373B2 · kind B2 · utility
0Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2021 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Jul 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/251
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a substrate including designated source or drain (source/drain) regions. An active source/drain is in the designated source/drain regions, and a source/drain cap liner is on an upper surface of the active source/drain. The semiconductor device further includes trench silicide regions completely filed with a silicide material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.