Patent · US Active

Single event upset tolerant memory device

US12045469B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Kumar Rahul · Andover, US
John Wuu · Fort Collins, US
Santosh Yachareni · San Diego, US
Nui Chong · San Jose, US
Cheang-Whang Chang · Mountain View, US

Key dates

Filing date	Dec 15, 2022
Grant date	Jul 23, 2024
Priority date	—
Expiry date	Jan 18, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG06F3/0673
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.