Circuitry to compensate for data drift in analog neural memory in an artificial neural network
US12056601B2 · kind B2 · utility
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5References
23Claims
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Key dates
| Filing date | Mar 26, 2020 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Oct 31, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system. For example, in one embodiment, a circuit is provided for compensating for drift error during a read operation, the circuit comprising a data drift monitoring circuit coupled to the array for generating an output indicative of data drift; and a bitline compensation circuit for generating a compensation current in response to the output from the data drift monitoring circuit and injecting the compensation current into one or more bitlines of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.