Managing sub-block erase operations in a memory sub-system
US12068037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2023 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Jul 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.