HEMT devices with reduced size and high alignment tolerance
US12068406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2021 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Feb 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/257
Abstract
A High Electron Mobility Transistor (HEMT) includes a source, a drain, a channel layer extending between the source and the drain, a barrier layer formed in contact with the channel layer, and extending between the source and the drain, and a gate formed in contact with, and covering at least a portion of, the barrier layer. The gate has gate edge portions and a gate central portion, and dielectric spacers may be formed over the gate edge portions, with the dielectric spacers having a first width therebetween proximal to the gate, and a second width therebetween distal from the gate, where the second width is longer than the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.