Integrated circuit device with improved reliability
US12074206B2 · kind B2 · utility
0Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Aug 30, 2021 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Nov 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.