Power supply tracking circuitry for embedded memories
US12094513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2022 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Apr 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate comprises a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.