Non-volatile memory with suspension period during programming
US12100461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Dec 2, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To remedy short term data retention issues, a system creates a gate to channel voltage differential for non-volatile memory cells between programming and verifying in order to accelerate the effects of the short term data retention issue. That is, the gate to channel voltage differential will accelerate the migrating of electrons out of shallow traps. In some embodiments, the gate to channel voltage differential comprises a higher voltage at the channel in comparison to the gate. In some embodiments, the programming comprises applying doses of a programming signal and the gate to channel voltage differential is only created for a subset of the time periods between doses of the programming signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.