Vertical transistor fabrication for memory applications
US12108604B2 · kind B2 · utility
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3References
10Claims
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Assignee
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Key dates
| Filing date | Sep 20, 2021 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Feb 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67742
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.