Manufacturing method of memory device
US12108691B2 · kind B2 · utility
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3References
7Claims
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Key dates
| Filing date | May 26, 2023 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | May 26, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.