Scan chain compression for testing memory of a system on a chip
US12112818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Dec 12, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.