MOS transistor having substantially parallelepiped-shaped insulating spacers
US12125899B2 · kind B2 · utility
0Cited by
10References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 19, 2021 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Feb 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.