Patent · US Active

Crested barrier device and synaptic element

US12141688B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Applied Materials, Inc. · US

Inventors

Milan Pesic · Berlin, DE
Shruba Gangopadhyay · San Jose, US
Muthukumar Kaliappan · Fremont, US
Michael Haverty · Mountain View, US

Key dates

Filing date	Jul 20, 2021
Grant date	Nov 12, 2024
Priority date	—
Expiry date	Jan 17, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH10B63/845
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A crested barrier memory device may include a first electrode, a first self-rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately −0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.