Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate using a dummy area
US12144172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2022 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Aug 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
Abstract
A method of forming a device on a semiconductor substrate having first, second, third and dummy areas, includes recessing the substrate upper surface in the first, second and dummy areas, forming a first conductive layer over the substrate, removing the first conductive layer from the third area and a second portion of the dummy area, forming a first insulation layer over the substrate, forming first trenches through the first insulation layer and into the substrate in the third area and the second portion of the dummy area, forming second trenches through the first insulation layer, the first conductive layer and into the substrate in the first and second areas and a first portion of the dummy area, and filling the first and second trenches with insulation material. Then, memory cells are formed in the first area, HV devices in the second area and logic devices in the third area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.