Patent · US Active

Transistors, memory cells, and arrangements thereof

US12148734B2 · kind B2 · utility

0Cited by

3References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Sarah Atanasov · Beaverton, US
Abhishek A. Sharma · Hillsboro, US
Bernhard Sell · Dresden, DE
Chieh-Jen Ku · Hillsboro, US
Elliot N. Tan · Portland, US
Hui Jae Yoo · Hillsboro, US
Noriyuki Sato · Hillsboro, US
Travis W. Lajoie · Forest Grove, US
Van H. Le · Portland, US
Thoe Michaelos · Portland, US

Key dates

Filing date	Dec 10, 2020
Grant date	Nov 19, 2024
Priority date	—
Expiry date	Jan 30, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/6728
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.