Thin film transistors having a backside channel contact for high density memory

US12150297B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Noriyuki Sato · Hillsboro, US
• Sarah Atanasov · Beaverton, US
• Abhishek A. Sharma · Hillsboro, US
• Bernhard Sell · Dresden, DE
• Chieh-Jen Ku · Hillsboro, US
• Arnab Sen Gupta · Hillsboro, US
• Matthew V. Metz · Portland, US
• Elliot N. Tan · Portland, US
• Hui Jae Yoo · Hillsboro, US
• Travis W. Lajoie · Forest Grove, US
• Van H. Le · Portland, US
• Pei-Hua Wang · Beaverton, US

Key dates

• Filing date: Dec 21, 2020
• Grant date: Nov 19, 2024
• Expiry date: Mar 19, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6757

Abstract

An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.