Molded direct contact interconnect structure without capture pads and method for the same
US12170261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2023 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | May 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/21
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.