Method for fabricating electronic package
US12176327B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2023 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Apr 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.