Patent · US Active

Semiconductor package with power electronics carrier having trench spacing adapted for delamination

US12183667B2 · kind B2 · utility

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0References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Scherl · Regensburg, DE
Adrian Lis · Regensburg, DE
Christian Neugirg · Regensburg, DE

Key dates

Filing date	Jan 20, 2022
Grant date	Dec 31, 2024
Priority date	—
Expiry date	Jun 24, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH01L23/3735
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor package includes a first power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the first power electronics carrier, and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package, a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.