Peter Scherl
17Patents
2h-index
27Co-inventors
50Inventor score
Filing activity: Sep 30, 2009 → Jan 20, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9633303B2 | Smart card module arrangement | Emerging Cross-Sectional Technologies | 4 | Active |
| US10566309B2 | Multi-purpose non-linear semiconductor package assembly line | Electricity | 3 | Active |
| US8640961B2 | Transponder inlay with antenna breaking layer for a document for personal identification, and a method for producing a transponder inlay | Emerging Cross-Sectional Technologies | 2 | Active |
| US9355984B2 | Electronic device and method for fabricating an electronic device | Electricity | 1 | Active |
| US11037856B2 | Semiconductor chip package comprising a leadframe connected to a substrate and a semiconductor chip, and a method for fabricating the same | Electricity | 1 | Active |
| US12183667B2 | Semiconductor package with power electronics carrier having trench spacing adapted for delamination | Electricity | 0 | Active |
| US11302668B2 | Multi-purpose non-linear semiconductor package assembly line | Electricity | 0 | Active |
| US9780053B2 | Method of forming a bondpad and bondpad | Electricity | 0 | Active |
| US11652084B2 | Flat lead package formation method | Electricity | 0 | Active |
| US8272574B2 | Document for personal identification having protection against external manipulations and a method for producing | Emerging Cross-Sectional Technologies | 0 | Active |
| US12300643B2 | Solder stop feature for electronic devices | Electricity | 0 | Active |
| US8684273B2 | Cover structure with integrated chip and antenna | Emerging Cross-Sectional Technologies | 0 | Active |
| US9756726B2 | Electronic device and method of fabricating an electronic device | Emerging Cross-Sectional Technologies | 0 | Active |
| US12224222B2 | Semiconductor package having a thermally and electrically conductive spacer | Electricity | 0 | Active |
| US9141902B2 | Smart card module for a smart card | Physics | 0 | Active |
| US9224695B2 | Chip arrangement and a method for manufacturing a chip arrangement | Electricity | 0 | Active |
| US11631628B2 | Semiconductor chip package comprising substrate, semiconductor chip, and leadframe and a method for fabricating the same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.