Stacked field-effect transistors

US12183740B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ruilong Xie · Niskayuna, US
• Kangguo Cheng · Schenectady, US
• Curtis S. Durfee · Schenectady, US
• Jay William Strane · Wappingers Falls, US
• Min Gyu Sung · Yongsan-gu, KR
• Julien Frougier · Albany, US
• Chanro Park · Clifton Park, US

Key dates

• Filing date: Jun 6, 2022
• Grant date: Dec 31, 2024
• Expiry date: Aug 18, 2043

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B82Y10/00
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top device, a bottom device, and a transition region between the top device and the bottom device. The transition region includes a plurality of inner spacers and a first inter-layer dielectric (ILD). The ILD is formed between each of the plurality of inner spacers. The top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between inner spacers. The second channel sheet thickness is larger than both the first channel sheet thickness and the first distance.