Three-dimensional memory devices with reduced cell interference and fabrication methods thereof
US12185536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2021 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Apr 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
Embodiments of a three-dimensional (3D) memory device and method for forming the 3D memory device are provided. In an example, the 3D memory device includes a plurality of conductor layers extending over a substrate, a channel structure vertically extending through the conductor layers to the substrate, and a source structure extending through the conductor layers to the substrate. The channel structure may include a blocking layer having a plurality of blocking portions disconnected from one another. Each of the blocking portions may include (i) a vertical blocking portion under a respective conductor layer, and (ii) at least one lateral blocking portion covering a respective lateral surface of the respective conductor layer. The channel structure may also include a memory layer having a plurality of memory portions disconnected from one another, each of the memory portions under and in contact with the respective vertical blocking portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.