Fabricating three-dimensional semiconductor structures

US12193231B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventors

• Soo Doo Chae · Albany, US
• Karthikeyan Pillai · Albany, US
• Lior Huli · Albany, US
• Na Young Bae · Albany, US
• Hojin Kim · Seoul, KR

Key dates

• Filing date: Sep 10, 2021
• Grant date: Jan 7, 2025
• Expiry date: Mar 24, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/10

Abstract

In certain embodiments, a method of fabricating a device includes forming, on a substrate, a layer stack of alternating layers of a first spin-on material and a second spin-on material. Each layer of the first spin-on material and the second spin-on material is formed by spin-on deposition. The method includes etching first openings through the layer stack and filling the first openings with a third material. The method includes etching second openings through the layer stack, removing the first spin-on material from the layer stack, and replacing the first spin-on material with a fourth material. The fourth material is a first metal-containing material.