Semiconductor device including gate spacer with tilted portion and method of manufacturing thereof
US12198984B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 30, 2024 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Jan 30, 2044 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.