Process window control for gate formation in semiconductor devices
US12199151B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 30, 2024 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Jan 30, 2044 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.