Elevationally-extending transistors, devices comprising elevationally-extending transistors, and methods of forming a device comprising elevationally-extending transistors
US12199182B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2021 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Feb 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.