Integrated circuitry comprising a memory array comprising strings of memory cells and method used in forming a memory array comprising strings of memory cells

US12200929B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Collin Howder · Boise, US
• M. Jared Barclay · Middleton, US
• Bhavesh Bhartia · Singapore, SG
• Chet E. Carter · Boise, US
• John D. Hopkins · Meridian, US
• Andrew Li · Boise, US
• Haoyu Li · Lo Wu, CN
• Alyssa N. Scarbrough · Boise, US
• Grady S. Waldo · Boise, US

Key dates

• Filing date: Aug 23, 2021
• Grant date: Jan 14, 2025
• Expiry date: Feb 6, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/27

Abstract

Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another. The lower portion comprises a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack. Other embodiments, including method, are disclosed.