Testing of analog neural memory cells in an artificial neural network

US12205655B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Hieu Van Tran · San Jose, US
• Thuan Vu · San Jose, US
• Stephen Trinh · San Jose, US
• Stanley Hong · Palo Alto, US
• Anh Ly · San Jose, US
• Steven Lemke · Boulder Creek, US
• Nha Thanh Nguyen · Shoreline, US
• Vipin Tiwari · Dublin, US
• Nhan Do · Saratoga, US

Key dates

• Filing date: Jun 15, 2022
• Grant date: Jan 21, 2025
• Expiry date: Jun 15, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/5006
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In one example, a method of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, comprises asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.