Hybrid smart verify for QLC/TLC die
US12205657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2022 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Apr 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5649
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.