Semiconductor assembly comprising a 3D block and method of making the same
US12205881B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2023 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Dec 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1058
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making an assembly or package comprising 3D blocks may include forming a conductive element horizontally oriented over a first carrier, forming support material around the conductive element, and singulating the conductive element and the support material to form a plurality of 3D blocks. The method may further include rotating each of the plurality of 3D blocks and mounting the plurality of 3D blocks over a second carrier with the conductive traces of the 3D blocks vertically oriented to form a vertically oriented conductive element. A plurality of components may be disposed laterally offset from each of the plurality of 3D blocks, an encapsulant may be disposed thereover s to form a reconstituted panel that may be singulated to form a plurality of individual assemblies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.