Method of forming a metal liner for interconnect structures
US12211743B2 · kind B2 · utility
0Cited by
5References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 3, 2021 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Feb 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.