Profile shaping for control gate recesses
US12211908B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Sep 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.