Wafer structure and semiconductor device
US12224256B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2022 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Aug 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.