Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)
US12235720B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2020 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Dec 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.