Two transistor memory cell using stacked thin-film transistors

US12238913B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Abhishek A. Sharma · Hillsboro, US
• Juan G. Alzate-Vinasco · Tigard, US
• Fatih Hamzaoglu · Portland, US
• Bernhard Sell · Dresden, DE
• Pei-Hua Wang · Beaverton, US
• Van H. Le · Portland, US
• Jack T. Kavalieros · Portland, US
• Tahir Ghani · Portland, US
• Umut Arslan · Hillsboro, US
• Travis W. Lajoie · Forest Grove, US
• Chieh-Jen Ku · Hillsboro, US

Key dates

• Filing date: Jan 31, 2023
• Grant date: Feb 25, 2025
• Expiry date: Jan 31, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/181
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.