Command address fault detection using a parity pin
US12242343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2022 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Dec 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.