Self-aligned interconnect structures and methods of fabrication

US12266570B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Kimin Jun · Hillsboro, US
• Souvik Ghosh · Santa Clara, US
• Willy Rachmady · Beaverton, US
• Ashish Agrawal · Hillsboro, US
• Siddharth Chouksey · Portland, US
• Jessica M. Torres · Portland, US
• Jack T. Kavalieros · Portland, US
• Matthew V. Metz · Portland, US
• Ryan Keech · Portland, US
• Koustav Ganguly · Beaverton, US
• Anand S. Murthy · Beaverton, US

Key dates

• Filing date: Dec 23, 2020
• Grant date: Apr 1, 2025
• Expiry date: May 16, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.