Neural network classifier using array of three-gate non-volatile memory cells
US12283314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2024 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Apr 24, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.