Gate-all-around integrated circuit structures having insulator substrate
US12294006B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2019 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Aug 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.