Method of manufacturing a semiconductor device having corner spacers adjacent a fin sidewall
US12294023B2 · kind B2 · utility
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18References
20Claims
0Family size
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Key dates
| Filing date | Aug 9, 2022 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Oct 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.