Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches

US12306754B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Jagadish B. Kotra · Austin, US
• John Kalamatianos · Boxborough, US
• Paul James Moyer · Fort Collins, US
• Nicholas Dean Lance · Windsor, US
• Sriram Srinivasan · Sammamish, US
• Patrick J. Shyvers · Fort Collins, US
• William L. Walker · Fort Collins, US

Key dates

• Filing date: Dec 20, 2022
• Grant date: May 20, 2025
• Expiry date: Feb 4, 2043

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/1044
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An entry of a last level cache shadow tag array to track pending last level cache misses to private data in a previous level cache (e.g., an L2 cache), that also are misses to an exclusive last level cache (e.g., an L3 cache) and to the last level cache shadow tag array. Accordingly, last level cache miss status holding registers need not be expended to track cache misses to private data that are already being tracked by a previous level cache miss status holding register. Additionally or alternatively, up to a threshold number of last level cache pending misses to the same shared data from different processor cores are tracked in the last level cache shadow tag array, and any additional last level cache pending misses are tracked in a last level cache miss status holding register.