Silicon-on-insulator semiconductor device with a static random access memory circuit
US12328858B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 5, 2023 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Oct 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.