Liner for V-NAND word line stack

US12328872B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Jacqueline S. Wrench · San Jose, US
• Yixiong Yang · San Jose, US
• Yong Wu · Sunnyvale, US
• Wei V. Tang · Santa Clara, US
• Srinivas Gandikota · Santa Clara, US
• Yongjing Lin · San Jose, US
• Karla M Bernal Ramos · San Jose, US
• Shih Chung Chen · Hsinchu, TW

Key dates

• Filing date: Sep 9, 2022
• Grant date: Jun 10, 2025
• Expiry date: Sep 13, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76876
• WIPO field: Surface technology, coating
• WIPO sector: Chemistry

Abstract

Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an α-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).