Non-linear polar material based multi-capacitor high density bit-cell

US12334127B2 · kind B2 · utility

Assignee

• Kepler Computing Inc. · US

Inventors

• Rajeev Kumar Dokania · Beaverton, US
• Mustansir Yunus Mukadam · Seattle, US
• Erik Unterborn · Cary, US
• Pramod Kolar · Cary, US
• Amrita Mathuriya · Portland, US
• Debo Olaosebikan · San Francisco, US
• Tanay Gosavi · Portland, US
• Noriyuki Sato · Hillsboro, US
• Sasikanth Manipatruni · Ithaca, US

Key dates

• Filing date: Jan 30, 2023
• Grant date: Jun 17, 2025
• Expiry date: May 31, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/682
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.